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SN74AUC16501

Features: ` Member of the Texas Instruments Widebus™ Family` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mode Operation` Sub-1-V Operable` Max tpd of 2 ns at 1.8 V` Low Power Consumption, 10 mA at 1.8 V` ±8-...

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SeekIC No. : 004498470 Detail

SN74AUC16501: Features: ` Member of the Texas Instruments Widebus™ Family` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mo...

SN74AUC16501 Data Sheet

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Part Number:
SN74AUC16501
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Upload time: 2025/12/24

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Product Details

Description



Features:

` Member of the Texas Instruments Widebus™ Family
` Optimized for 1.8-V Operation and Is 3.6-V I/O
  Tolerant to Support Mixed-Mode Signal Operation
` Ioff Supports Partial-Power-Down Mode Operation
` Sub-1-V Operable
` Max tpd of 2 ns at 1.8 V
` Low Power Consumption, 10 mA at 1.8 V
` ±8-mA Output Drive at 1.8 V
` Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II
` ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Symbol Parameter MIN MAX Units
VCC Supply voltage range -0.5 3.6 V
VI Input voltage range(2) -0.5 3.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) -0.5 3.6 V
VO Output voltage range(2) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0   -50 mA
IOK Output clamp current VO < 0   -50 mA
IO Continuous output current   ±20 mA
ICC Continuous current through VCC or GND   ±100 mA
IANG Package thermal impedance(3) DCT package   64 °C/W
DCU package   48
YEP/YZP package   42
TSTG Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

This SN74AUC16501 18-bit universal bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

SN74AUC16501 Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

SN74AUC16501 Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables arecomplementary (OEAB is active high and OEBA is active low).




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