SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to4.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to4.6 V Voltage range applied to any...
SN74AVC32373: SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to4.6 VInput voltage range, VI (see Note 1) . . . . . . . . ....
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A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCE) Circuitry Technology and Applications, literature number SCEA009.This SN74AVC32373 32-bit transparent D-type latch with is operational from 1.2-V or 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVC32373 can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input of SN74AVC32373 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
This SN74AVC32373 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74AVC32373 is characterized for operation from 40°C to 85°C.