SN74CBTU4411

Supply voltage range, V_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Control input voltage range, V_IN (see Notes 1 and 2) . . . . . . .. . −0.5 V to 2.5 V
Switch I/O voltage range, V_I/O (see Notes 1, 2, and 3) . . . . .. . . −0.5 V to 2.5 V
Control input clamp current, I_IK (V_IN < 0 or V_IN > 0) . . . . . . . . . . . . . . . ±50 mA
I/O port clamp current, I_I/OK (V_I/O < 0 or V_I/O > 0) . . . . . . . . . . . . . . . . ±50 mA
ON-state switch current, I_I/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Continuous current through V_DD or GND terminals . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, _JA (see Note 5) . . . . . . . . . . . . . . . . . . . TBD°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V_I and V_O are used to denote specific conditions for V_I/O.
4. I_I and I_O are used to denote specific conditions for I_I/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.

The SN74CBTU4411 is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (r_on). The device utilizes an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat r_on. The low and flat r_on allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising/falling edge skew. This allows the device to show optimal performance in DDR-II applications.

The SN74CBTU4411 is organized as an 11-bit 1-of-4 multiplexer/demultiplexer with a single switch-enable (EN) input.When EN is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the disabled channels are connected to VBIAS through a 400 resistor. DQS_EN determines the output voltage for the disabled D10 ports. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, the disabled D10 ports are connected to an internal voltage (V_BIAS__DQS) source, which is approximately equal to 0.7 V_DD.

When EN of the SN74CBTU4411 is high, all the channels are disabled. Ports D0 to D9 are connected to V_BIAS. For the D10 port, the disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, this voltage is V_DD.

The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. The EN and TC inputs of the SN74CBTU4411 determine the internal termination for S0 and S1 inputs. When EN is low, the termination is determined by the TC input. When both EN and TC are low, termination resistors are disconnected from the S inputs. When EN is low and TC is high, both pullup and pulldown resistors are connected to the S inputs. When EN is high, only the pulldown termination resistors are connected to the S inputs, regardless of the voltage level at the TC input.