SN74FB2032

    The SN74FB2032 device is a 9-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments and to perform bus arbitration. It is designed specifically to be compatible with IEEE Std 1194.1-1991.

    The SN74FB2032 B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have minimum output edge rates of 2 ns. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V, the B port is turned off.

    The SN74FB2032 A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable, OEA, is high. When OEA is low or when V_CC is less than 2.1 V, the A outputs are in the high-impedance state.

    The SN74FB2032 A-port data is latched when the latch enable (LE) is high. When LE is low, the latches are transparent.

    The Futurebus protocol logic can be activated by taking COMPETE low. The module (device) then compares SN74FB2032 A data (arbitration number) against the A data of another identical module also connected to the B arbitration bus, and sets WIN high if the A data is greater than the A data of the other module (i.e., has higher priority). A8 and B8 are the most-significant bits, and A1 and B1 are the least-significant bits. If OEB is high and OEB is low during this operation, and the A bus of the first module wins priority, the A bus asserts its arbitration number on the B-arbitration bus.

    AP and BP are the bus-parity bits. The winning module SN74FB2032 can assert BP low if its parity bit (AP) is high.

    In a typical operating sequence, a Futurebus arbitration controller latches its arbitration number into the A port and waits for the results of a competition. When the competition is complete, and if the controller's arbitration number did not win, the controller reads back the current value of the B bus (by taking OEA high) and determines the winning arbitration number. SN74FB2032 allows the module to change its arbitration number for the next competition cycle, if desired.

    Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus. TMS and TCK are not connected and TDI is shorted to TDO.

    BIAS V_CC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V_CC is not connected. BG V_CC and BG GND are the supply inputs for the bias generator.

    The SN74FB2032 is characterized for operation from 0°C to 70°C.