SN74LVC125A

Features:

* EPICE (Enhanced-Performance Implanted
   CMOS) Submicron Process
* ESD Protection Exceeds 2000 V Per
   MIL-STD-883, Method 3015; Exceeds 200 V
   Using Machine Model (C = 200 pF, R = 0)
* Latch-Up Performance Exceeds 250 mA Per
   JESD 17
* Typical V_OLP (Output Ground Bounce)
   < 0.8 V at V_CC = 3.3 V, TA = 25
* Typical V_OHV (Output VOH Undershoot)
   > 2 V at V_CC = 3.3 V, TA = 25
* Inputs Accept Voltages to 5.5 V
* Package Options Include Plastic
   Small-Outline (D), Shrink Small-Outline
   (DB), and Thin Shrink Small-Outline (PW)
   Packages


Pinout




Specifications

Supply voltage range, V_CC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .0.5 V to 6.5 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .0.5 V to 6.5 V
Output voltage range, V_O (see Notes 1 and 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .±100 mA
Package thermal impedance, _JA (see Note 3): D package  . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .127/W
                                                                          DB package  . . . . . . . . . . . . . . . . . . . . .  . . ..... . . . . . . .158/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..... . .170/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 to 150

Description

This quadruple bus buffer gate SN74LVC125A is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, SN74LVC125A OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74LVC125A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN74LVC125A is characterized for operation from 40 to 85.