SN74LVC161284

Supply voltage range: V_CC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
                                    V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input and output voltage range, V_I and V_O: Cable side (see Notes 1 and 2) . . . . .  . . . . . 2 V to 7 V
                                                                      Peripheral side (see Note 1) . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, I_O: Except PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
                                                  PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . ±100 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Output high sink current, I_SK (V_O = 5.5 V and V_CC CABLE = 3 V) . . . . . . . . . . . . . . . . . . .  . . . . . . 65 mA
Package thermal impedance, _JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . .  . . . . 89°C/W
                                                                          DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than 0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51.

The SN74LVC161284 is designed for 3-V to 3.6-V V_CC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The SN74LVC161284 output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kW integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above V_CC CABLE. If V_CC CABLE is off, PERI LOGIC OUT is set to low.

The device SN74LVC161284 has two supply voltages. V_CC is designed for 3-V to 3.6-V operation. V_CC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when V_CC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.