Features: `Member of the Texas Instruments Widebus™ Family`Operates From 1.65 V to 3.6 V`Inputs Accept Voltages to 5.5 V`Max tpd of 4.2 ns at 3.3 V`Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C`Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C...
SN74LVC16373A: Features: `Member of the Texas Instruments Widebus™ Family`Operates From 1.65 V to 3.6 V`Inputs Accept Voltages to 5.5 V`Max tpd of 4.2 ns at 3.3 V`Typical VOLP (Output Ground Bounce) < 0.8...
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`Member of the Texas Instruments Widebus™ Family
`Operates From 1.65 V to 3.6 V
`Inputs Accept Voltages to 5.5 V
`Max tpd of 4.2 ns at 3.3 V
`Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
`Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
`Ioff Supports Partial-Power-Down Mode Operation
`Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
`Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
`ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
| MIN | MAX | UNIT | |||
| VCC | Supply voltage range | 0.5 | 6.5 | V | |
| VI | Input voltage range(2) | 0.5 | 6.5 | V | |
| VO | Voltagerangeappliedtoanyoutputinthehighimpedanceorpoweroffstate(2) | 0.5 | 6.5 | V | |
| VO | Voltage range applied to any output in the high or low state(2) (3) | 0.5 | VCC + 0.5 | V | |
| IIK | Input clamp current | VI0 | 50 | mA | |
| IOK | Output clamp current | VO0 | 50 | mA | |
| IO | Continuous output current | ±50 | mA | ||
| Continuous current through each VCC or GND | ±100 | mA | |||
| JA | Package thermal impedance(4) | DGG package | /W | ||
| DGV package | |||||
| DL package | |||||
| GQL/ZQL package | |||||
| GRD/ZRD package | |||||
| Tstg | Storage temperature range | 65 | 150 | ||
This 16-bit transparent D-type latch SN74LVC16373A is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.