SN74LVC2G132

Features:

` Available in Texas Instruments NanoStar™ and NanoFree™ Packages
` Supports 5-V V_CC Operation
` Inputs Accept Voltages to 5.5 V
` Max t_pd of 5.3 ns at 3.3 V
` Low Power Consumption, 10-A Max I<sub>CC</sub>
` ±24-mA Output Drive at 3.3 V
` Typical V<sub>OLP</sub> (Output Ground Bounce) <0.8 V at V<sub>CC</sub> = 3.3 V, T<sub>A</sub> = 25°C
` Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
` I<sub>off</sub> Supports Partial-Power-Down Mode Operation
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Protection Exceeds JESD 22
  2000-V Human-Body Model (A114-A)
  200-V Machine Model (A115-A)
  1000-V Charged-Device Model (C101)


Specifications

			MIN	MAX	UNIT
VCC	Supply voltage range		0.5	6.5	V
VI	Input voltage range(2)		0.5	6.5	V
VO	Voltage range applied to any output in the high-impedance or power-off state(2)		0.5	6.5	V
VO	Voltage range applied to any output in the high or low state(2) (3)		0.5	VCC + 0.5	V
IIK	Input clamp current	VI< 0		50	mA
IOK	Output clamp current	VO< 0		50	mA
IO	Continuous output current			±50	mA
	Continuous current through VCC or GND			±100	mA
JA	Package thermal impedance(4)	DCT package		220	°C/W
		DCU package		227
		YEP/YZP package		102
Tstg	Storage temperature range		65	150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V_CC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7


Description

This SN74LVC2G132 dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A × B or Y = A +B  in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (V_T+) and negative-going (V_T-) signals.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device SN74LVC2G132 can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device SN74LVC2G132 is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.