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SN74LVC2G80

Features: Available in the Texas InstrumentsNanoStar(TM) and NanoFree(TM) PackagesSupports 5-V VCC OperationInputs Accept Voltages to 5.5 VMax tpd of 4.2 ns at 3.3 VLow Power Consumption, 10-A Max ICCTypical VOLP (Output Ground Bounce)< 0.8 V at V = 3.3 VCC, TA = 25°CTypical VOHV (Output VOH Un...

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SeekIC No. : 004499318 Detail

SN74LVC2G80: Features: Available in the Texas InstrumentsNanoStar(TM) and NanoFree(TM) PackagesSupports 5-V VCC OperationInputs Accept Voltages to 5.5 VMax tpd of 4.2 ns at 3.3 VLow Power Consumption, 10-A Max I...

SN74LVC2G80 Data Sheet

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Part Number:
SN74LVC2G80
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Available in the Texas Instruments
NanoStar(TM) and NanoFree(TM) Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Low Power Consumption, 10-A Max ICC
Typical VOLP (Output Ground Bounce)
< 0.8 V at V = 3.3 VCC, T A = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 VCC at V = 3.3 V, TA = 25°C
Ioff Feature Supports Partial-Power-Down
Mode Operation
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Description

This dual positive-edge-triggered D-type flip-flop SN74LVC2G80 is designed for 1.65-V to 5.5-V VCC operation.

When data at the SN74LVC2G80 data (D) input meets the setup time requirement, the data is transferred to the Q output on the ositive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar(TM) and NanoFree(TM) package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device SN74LVC2G80 is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,off off preventing damaging current backflow through the device when it is powered down.




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