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SN74LVC827

Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C•Latch-Up Performance Exceeds 250 mA Per JEDEC Standa...

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SeekIC No. : 004499364 Detail

SN74LVC827: Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Under...

SN74LVC827 Data Sheet

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Part Number:
SN74LVC827
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages  


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6V
Input voltage range, VI (see Note 1) . . . . . . . . . . . .. . . .  . . . . .. . . . . . . . . . .  . . . . .0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . .  . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at TA = 55°C (in still air)(see Note 3):DB package  . .  . 0.65 W
                                                                                                                     DW package  . . . . 1.7 W
                                                                                                                     PW package  . . . . .0.7 W 
Storage temperature range ,Tstg . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .  . . 65°C to 150°C 


Description

This 10-bit buffer/bus driver SN74LVC827 is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC827 provides a high-performance bus interface for wide data paths or buses carrying parity.

The SN74LVC827 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The SN74LVC827 provides true data at its outputs.

To ensure the high-impedance state during power up or power down, SN74LVC827 OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC827 is characterized for operation from 40°C to 85°C.




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