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SN74LVTH162373

Features: ` Members of the Texas Instruments Widebus™ Family` State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation` Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required` Support Mixed-Mode Signal Ope...

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SeekIC No. : 004499459 Detail

SN74LVTH162373: Features: ` Members of the Texas Instruments Widebus™ Family` State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation` Output Ports Have E...

SN74LVTH162373 Data Sheet

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Part Number:
SN74LVTH162373
Supply Ability:
5000

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Product Details

Description



Features:

` Members of the Texas Instruments
    Widebus™ Family
` State-of-the-Art Advanced BiCMOS
    Technology (ABT) Design for 3.3-V
    Operation and Low Static-Power
    Dissipation
` Output Ports Have Equivalent 22- Series
    Resistors, So No External Resistors Are
    Required
` Support Mixed-Mode Signal Operation
    (5-V Input and Output Voltages With
     3.3-V VCC)
` Support Unregulated Battery Operation
    Down to 2.7 V
` Typical VOLP (Output Ground Bounce)
     < 0.8 V at VCC = 3.3 V, TA = 25°C
` Ioff and Power-Up 3-State Support Hot
   Insertion
` Bus Hold on Data Inputs Eliminates the
    Need for External Pullup/Pulldown
    Resistors
` Distributed VCC and GND Pin Configuration
     Minimizes High-Speed Switching Noise
` Flow-Through Architecture Optimizes PCB
    Layout
` Latch-Up Performance Exceeds 500 mA Per
     JESD 17
` ESD Protection Exceeds 2000 V Per
    MIL-STD-883, Method 3015; Exceeds 200 V
    Using Machine Model (C = 200 pF, R = 0)
` Package Options Include Plastic Shrink
    Small-Outline (DL) and Thin Shrink
    Small-Outline (DGG) Packages and 380-mil
   Fine-Pitch Ceramic Flat (WD) Package
   Using 25-mil Center-to-Center Spacings


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 0.5 V to4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 30mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to150°C


Description

The SN74LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices SN74LVTH162373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.

About SN74LVTH162373,A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LVTH162373 outputs, which are designed to source or sink up to 12 mA, include equivalent 22-W series resistors to
reduce overshoot and undershoot.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices SN74LVTH162373 are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

About SN74LVTH162373,The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH162373 is characterized for operation over the full military temperature range of 55°C to 125°C.

The SN74LVTH162373 is characterized for operation from 40°C to 85°C.




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