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SN74LVTH573

Features: · Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)· Support Unregulated Battery Operation Down to 2.7 V· Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C· Ioff and Power-Up 3-State Support Hot Insertion· Bus Hold on Data Inputs Eli...

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SeekIC No. : 004499501 Detail

SN74LVTH573: Features: · Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)· Support Unregulated Battery Operation Down to 2.7 V· Typical VOLP (Output Ground Bounce) <0.8 V at ...

SN74LVTH573 Data Sheet

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Part Number:
SN74LVTH573
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

· Support Mixed-Mode Signal Operation
    (5-V Input and Output Voltages With
    3.3-V VCC)
· Support Unregulated Battery Operation
    Down to 2.7 V
· Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
· Ioff and Power-Up 3-State Support Hot
    Insertion
· Bus Hold on Data Inputs Eliminates the
    Need for External Pullup/Pulldown
    Resistors
· Latch-Up Performance Exceeds 500 mA Per
    JESD 17
·ESD Protection Exceeds JESD 22
   − 2000-V Human-Body Model (A114-A)
   − 200-V Machine Model (A115-A)


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH573 . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 96 mA
SN74LVTH573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH573 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH573 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . −50 mA
Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
                                                    (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 58°C/W
                                                    (see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 78°C/W
                                                    (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 60°C/W
                                                     (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83°C/W
                                                      (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.


Description

These octal latches SN74LVTH573 are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight latches of the SN74LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

About SN74LVTH573,A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

SN74LVTH573,To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided by SN74LVTH573 to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices SN74LVTH573 are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.




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