SN74SSTEB32866

DescriptionThe SN74SSTEB32866 operates from a differential clock (CLK and CLK ). Data are registered at the crossing of CLK going high and CLK going low.The SN74SSTEB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,compares it with the data received on the DIM...

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SeekIC No. : 004499530 Detail

SN74SSTEB32866: DescriptionThe SN74SSTEB32866 operates from a differential clock (CLK and CLK ). Data are registered at the crossing of CLK going high and CLK going low.The SN74SSTEB32866 accepts a parity bit from ...

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Part Number:
SN74SSTEB32866
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Description

The SN74SSTEB32866 operates from a differential clock (CLK and CLK ). Data are registered at the crossing of CLK going high and CLK going low.The SN74SSTEB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,compares it with the data received on the DIMM-independent D-inputs (D2 D3, D5 D6, D8 D25 when C0 = 0 and C1 = 0; D2 D3, D5 D6, D8 D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.

Features of the SN74SSTEB32866 are:(1)Member of the Texas Instruments Widebus+  Family; (2)Pinout Optimizes DDR2 DIMM PCB Layout; (3)Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer; (4)Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption; (5)Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line; (6)Supports 1.5V and 1.8V Supply Voltage Range; (7)Differential Clock (CLK and CLK ) Inputs; (8)Supports LVCMOS Switching Levels on the Control and RESET Inputs; (9)Checks Parity on DIMM-Independent Data Inputs; (10)Able to Cascade With a Second SN74SSTEB32866; (11)Supports Industrial Temperature Range ( 40 ° C to 85 ° C).

The absolute maximum ratings of the SN74SSTEB32866 can be summarized as:(1)Supply voltage range 0.5 to 2.5 V; (2)Input voltage range (2) (3) 0.5 to V CC + 0.5 V; (3)Output voltage range (2) (3) 0.5 to V CC + 0.5 V; (4)Input clamp current, (V I < 0 or V I > V CC ) ± 50 mA; (5)Output clamp current, (V O < 0 or V O > V CC ) ± 50 mA; (6)Continuous output current (V O = 0 to V CC ) ± 50 mA; (7)Continuous current through each V or GND ± 100 mA.

If you want to know more information such as the electrical characteristics of SN74SSTEB32866 ,please download the datasheet in www.seekdatasheet.com .




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