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SN74SSTV32852

Features: Member of the Texas Instruments WidebusTM Family1-to-2 Outputs Support Stacked DDR DIMMsSupports SSTL_2 Data InputsOutputs Meet SSTL_2 Class II SpecificationsDifferential Clock (CLK andCLK ) InputsSupports LVCMOS Switching Levels on the RESET InputRESET Input Disables Differential InputR...

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SeekIC No. : 004499542 Detail

SN74SSTV32852: Features: Member of the Texas Instruments WidebusTM Family1-to-2 Outputs Support Stacked DDR DIMMsSupports SSTL_2 Data InputsOutputs Meet SSTL_2 Class II SpecificationsDifferential Clock (CLK andCLK...

SN74SSTV32852 Data Sheet

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Part Number:
SN74SSTV32852
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
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  • 15 Days
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Product Details

Description



Features:

Member of the Texas Instruments WidebusTM Family
1-to-2 Outputs Support Stacked DDR DIMMs
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II Specifications
Differential Clock (CLK and  CLK ) Inputs
Supports LVCMOS Switching Levels on the  RESET  Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces All Outputs Low
Pinout Optimizes DIMM PCB Layout
One Device Per DIMM Required
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
         2000-V Human-Body Model (A114-A)
         1000-V Charged-Device Model (C101)


Specifications

Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . .  . .. . 0.5 V to 3.6 V 
Input voltage range, VI (see Notes 1 and 2)  . . . . .  . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2)  . . . . ..0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . .  . . . . . . . . .  .. .50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ). . . . . . . . . . . . . .  . .  ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . .. . . ±50 mA
Continuous current through each VCC, VDDQ, or GND  . . . . . . .  . . .. . .±100 mA
Package thermal impedance, JA (see Note 3) . . . . . . . . . . . .. . . . . . . 36°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . ..65°C to 150°C


Description

This 24-bit to 48-bit registered buffer SN74SSTV32852 is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset ( RESET) input. All outputs are SSTL_2, Class II compatible.The SN74SSTV32852 operates from a differential clock (CLK and   CLK). Data are registered at the crossing of   CLK going high and CLK going low.

The device SN74SSTV32852 supports low-power standby operation. When  RESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when  RESET is low, all registers are reset and all outputs are forced low. The LVCMOS  RESET input always must be held at a valid logic high or low level.

To ensure defined outputs from the SN74SSTV32852 register before a stable clock has been supplied,  RESET must be held in the low state during power up.




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