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SN74SSTV32867

SpecificationsSupply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 3.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 a...

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SeekIC No. : 004499543 Detail

SN74SSTV32867: SpecificationsSupply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 3.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . ...

SN74SSTV32867 Data Sheet

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Part Number:
SN74SSTV32867
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Specifications

Supply voltage range, VCC or VDDQ  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2)  . . . . . . . . . . . . . . . . .  . . . . . .0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ)  . . . . . . . . . . . . . . . . . . . . . .  . . . . . .. . . . . .±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .. .. . . .±50 mA
Continuous current through each VCC, VDDQ, or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100 mA
Package thermal impedance, JA (see Note 3)  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .  . .. . . .40°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C


Description

This 26-bit registered buffer SN74SSTV32867 is designed for 2.3-V to 2.7-V VCC operation.

All SN74SSTV32867 inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTV32867 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

The device SN74SSTV32867 supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held at a valid logic high or low level.

To ensure defined outputs from the rSN74SSTV32867 egister before a stable clock has been supplied, RESET must be held in the low state during power up.




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