SN74VMEH22501A

` Member of the Texas Instruments Widebus<sup>TM</sup> Family
` UBT^TM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
` OEC<sup>TM</sup> Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference (EMI)
` Compliant With VME64, 2eVME, and 2eSST Protocols
` Bus Transceiver Split LVTTL Port Provides Feedback Path for Control and Diagnostics Monitoring
` I/O Interfaces Are 5-V Tolerant
` B-Port Outputs (−48 mA/64 mA)
` Y and A-Port Outputs (−12 mA/12 mA)
` I<sub>off</sub>, Power-Up 3-State, and BIAS V<sub>CC</sub> Support Live Insertion
` Bus Hold on 3A-Port Data Inputs
` 26- Equivalent Series Resistor on 3A Ports and Y Outputs
` Flow-Through Architecture Facilitates Printed Circuit Board Layout
` Distributed VCC and GND Pins Minimize High-Speed Switching Noise
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Protection Exceeds JESD 22
-2000-V Human-Body Model (A114-A)
-200-V Machine Model (A115-A)
-1000-V Charged-Device Model (C101)

Supply voltage range, V_CC and BIAS V_CC..................... −0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) ..............................−0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V_O (see Note 1) ................................−0.5 V to 7 V
Voltage range applied to any output in the high or low state, V_O
(see Note 1): 3A port or Y output ......................−0.5 V to V_CC + 0.5 V
B port .....................................................−0.5 V to 4.6 V
Output current in the low state, I_O: 3A port or Y output ...........50 mA
B port ..............................100 mA
Output current in the high state, I_O:3A port or Y output......... −50 mA
B port ............................−100 mA
Input clamp current, I_IK (V_I < 0) ...............................................−50 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC): B port ...........−50 mA
Package thermal impedance, _JA (see Note 2): DGG package....70/W
DGV package.... 58/W
GQL package ....42/W
Storage temperature range, T_stg....................................−65 to 150


† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V V_CC operation with 5-V tolerant inputs. The UBTtransceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320^† backplane topologies.

The SN74VMEH22501A is pin-for-pin capatible to the VMEH22501, but operates at a wider operating temperature (−40°C to 85°C) range. High-speed backplane operation is a direct result of the improved OEC^TM circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (1/2 V_CC ±50 mV) for increased noise immunity.

SN74VMEH22501A support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.

Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.This device SN74VMEH22501A is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V_CC. The Ioff circuitry prevents damaging current to backflow through the device SN74VMEH22501A when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V_CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When V_CC is between 0 and 1.5 V, the device SN74VMEH22501A is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to V_CC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.