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SP489

PinoutSpecificationsVCC ........................................................................................ +7VInput VoltagesLogic ............................................................ 0.5V to (VCC +0.5V)Receiver ............................................................................

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SeekIC No. : 004500450 Detail

SP489: PinoutSpecificationsVCC ........................................................................................ +7VInput VoltagesLogic ............................................................ 0...

SP489 Data Sheet

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Part Number:
SP489
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Pinout

Connection Diagram


Specifications

VCC ........................................................................................ +7V
Input Voltages
Logic ............................................................ 0.5V to (VCC +0.5V)
Receiver ................................................................................ ±14V
Receiver Output Voltage .............................. 0.5V to (VCC +0.5V)
Input Currents
Logic .................................................................................. ±25mA
Storage Temperature ........................................ 65°C to +150°C
Power Dissipation
Plastic DIP ........................................................................ 375mW
(derate 7mW/°C above +70°C)
Small Outline .................................................................... 375mW
(derate 7mW/°C above +70°C)
Lead Temperature (soldering, 10 sec) ............................... 300°C


Description

The SP488 and SP489 are lowpower quad differential line receivers meeting RS-485 and RS-422 standards. The SP488 features a common receiver enable control; the SP489 provides independent receiver enable controls for each pair of receivers. Both feature tristate outputs and wide common mode input range. The receivers have a failsafe feature which forces a logic "1" output when receiver inputs are left floating. Both are available in 16pin plastic DIP and SOIC packages.




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