SP5730A

The SP5730A is one member of the SP5730 series.The  SP5730  is a single  chip frequency synthesiser designed for tuning systems up to 1.3GHz and is optimised for digital terrestrial applications.The RF preamplifier interfaces direct with the RF programmable divider, which is of MN+A construction so giving a step size equal to the loop comparison frequency and no prescaler phase noise degradation over the RF operating range.

Features of the SP5730A are:(1)complete 1.3GHz single chip system for digital terrestrial television applications; (2)selectable reference division ratio, compatible with (DTT) requirements; (3)optimised for low phase noise, with comparison frequencies up to 4MHz; (4)no RF prescaler; (5)selectable reference/comparison frequency output; (6)3.3 and 5V logic levels; (7)four switching ports; (8)ESD protection, (Normal ESD Handling procedures should be observed).The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, Fref, or phase comparator frequency, Fcomp, can be switched to the REF/COMP output providing a reference frequency for a second frequency synthesiser.

The absolute maximum ratings of the SP5730A can be summarized as:(1)supply voltage,Vcc:-0.3 to 7 V;(2)RF input voltages:2.5V;(3)storage temperature:-55 to 150;(4)all I/O port DC offsets:-0.3 Vcc+0.3 V;(5)power dissipation:83mW.The SP5730 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance.It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers The block diagram is shown in Figure 2.The RF input signal is fed to an internal preamplifier,which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider, which is of MN+A architecture, where the dual modulus prescaler is 8/9, the A counter is 3-bits, and the M counter is 12 bits.