SP5730

Features: • Complete 1·3 GHz Single Chip System for Digital Terrestrial Television Applications• Selectable Reference Division Ratio, Compatible with DTT Requirements• Optimised for Low Phase Noise, with Comparison Frequencies up to 4 MHz• No RF Prescaler• Selectable ...

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SeekIC No. : 004500505 Detail

SP5730: Features: • Complete 1·3 GHz Single Chip System for Digital Terrestrial Television Applications• Selectable Reference Division Ratio, Compatible with DTT Requirements• Optimised fo...

floor Price/Ceiling Price

Part Number:
SP5730
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2025/12/24

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Product Details

Description



Features:

• Complete 1·3 GHz Single Chip System for Digital Terrestrial Television Applications
• Selectable Reference Division Ratio, Compatible with DTT Requirements
• Optimised for Low Phase Noise, with Comparison Frequencies up to 4 MHz
• No RF Prescaler
• Selectable Reference/Comparison Frequency Output
• Four Selectable I2C Addresses
• I2C Fast Mode Compliant with 3·3V and 5V Logic Levels
• Four Switching Ports
• Functional Replacement for SP5659 (except ADC)
• Pin Compatible with SP5655
• Power Consumption 120mW with VCC = 5·5V, all Ports off
• ESD Protection 2kV min., MIL-STD-883B Method 3015 Cat.1 (Normal ESD handling procedures should be observed)




Application

• Digital Satellite, Cable and Terrestrial Tuning Systems
• Communications Systems




Pinout

  Connection Diagram


Specifications

All voltages are referred to VEE = 0V
Supply voltage, VCC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance
Chip to ambient, JA
Chip to case, JC

-0`3V to +7V
2`5Vp-p
-0`3 to VCC +0`3V
-0`3 to 6V
-55°C to +150°C
+150°C

80°C/W
20°C/W



Description

The SP5730 is a single chip frequency synthesiser designed for tuning systems up to 1·3GHz and is optimised for digital terrestrial applications. The RF preamplifier interfaces direct with the RF programmable divider, which is of MN1A construction so giving a step size equal to the loop comparison frequency and no prescaler phase noise degradation over the full RF operating range. The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, fREF, or phase comparator frequency, fCOMP, can be switched to the REF/ COMP output providing a reference for a second frequency synthesiser. The synthesiser is controlled via an 12C bus and is fast mode compliant. It can be hard wired to respond to one of four addresses to enable two or more synthesisers to be used on a common bus. The device contains four switching ports P0 - P3.




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