SP8854E

The SP8854E can operate with input frequencies up to 2·7GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8854E is mounted should be left as a continuous sheet of copper to form a low impedance ground plane. The ground pins 12 and 16 should be connected directly to the ground plane.

Pins such as VCC and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible, with a direct connection to the ground plane; suitable values are 10nF for the power supplies and <1nF for the RF input pin (a lower value should be used sufficient to give good decoupling at the RF frequency of  peration). A larger decoupling capacitor mounted as close as possible to pin 26 should be used to prevent modulation of VCC by the charge pump pulses. The RSET resistor should also be mounted close to the RSET pin to prevent noise pickup. The capacitor connected from the charge pump output should be a chip component with short connections to the SP8852E. All signals such as the programming inputs, RF IN, REFERENCE IN and the connections to the op-amp are best taken through the pc board adjacent to the SP8852D with through plated holes allowing connections to remote points without fragmenting the ground plane.

Supply voltage......................................................-0.3V to 16V
Operating temperature................................-55°C to+100°C
Storage temperature..................................-65°C to +150°C
Prescaler and reference input voltage........................2.5V p-p
Data inputs.............................................................VCC +0.3V
                   ..............................................................VEE -0.3V
Junction temperature.................................................+175°C

The SP8854E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other parts in the series are the SP8852E which is fully programmable, requiring tw0 16- bit words to set the RF and reference counters and the SP8855E which is fully programmable using hard wired links or switches.

The SP8854E is programmed using a 16-bit parallel data bus. Data is stored in an internal buffer. The 10-bit programmable reference divider is programmed by connecting the 10 programming pins either to ground or 15V. The device can therefore be programmed with a single transfer from the control microprocessor. Hard wired inputs can also control the FPD and FREF outputs and the control sense of the loop.