SSD1815B

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V_in and V_out be constrained to the range V_SS < or = (V _in or V_out) < or = V_DD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either V_SS or V_DD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.

This module SSD1815B determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin.

If D/C pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it low, the input at D7-D0 is interpreted as a Command and SSD1815B will be decoded and be written to the corresponding command register.

The parallel interface of SSD1815B consists of 8 bi-directional data pins (D7-D0), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The E(RD) input serves as data latch signal (clock) when high provided that CS1 and CS2 are low and high respectively. Refer to Figure 11 on page 27 for Parallel Interface Timing Diagram of 6800-series microprocessors.

In order to match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing of SSD1815B is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3.