SST31LH041

The SST31LH041 is a 512K x 8 CMOS flash memory bank combined with a 128K x 8 CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. The SST31LH041 device writes (SRAM or programs or erases flash) with a 3.0-3.6V power supply. The monolithic SST31LH041 device conforms to JEDEC standard pinouts and Software Data Protect (SDP) commands for x8 EEPROMs in TSOP packages.

Featuring high performance byte program, the flash memory bank provides a maximum byte program time of 20 sec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 8 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LH041 device has on-chip hardware and software data protection schemes. Designed, manufactured,and tested for a wide spectrum of applications, the SST31LH041 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST31LH041 operates as two independent memory banks with respective bank enable signals. The SRAM and Flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.

The SST31LH041 provides the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector Erase, Bank Erase, or Byte Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled erase or program cycle in the flash bank has commenced, the SRAM bank can be accessed for read or write.

The SST31LH041 device is suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LH041 device significantly improves performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LH041 inherently uses less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies,whose Erase and Program times increase with accumulated Erase/Program cycles.

The SST31LH041 device also improves flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LH041 device is offered in 32-pin and 40-pin TSOP packages. See Figure 1 for the pinouts.