SST89E516RD2-40-C-NJE

Operating Temperature Range :
Data Bus Width : 8 bit
Mounting Style : SMD/SMT
Program Memory Size : 64 KB
Data RAM Size : 1 KB
Package / Case : PLCC-44
Maximum Clock Frequency : 40 MHz
On-Chip ADC : No
Operating Supply Voltage : 2.7 V to 3.6 V
Core : FlashFlex
Processor Series : SST89C


Description

The SST89E516RD2-40-C-NJE is member of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST's patented and proprietary SuperFlash CMOS semiconductor process technology.The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST's customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.

The SST89E516RD2-40-C-NJEs come with 72 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 64 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.The 8-KByte secondary block can be mapped to the lowest location of the 64 KByte address space; SST89E516RD2-40-C-NJE can also be hidden from the program counter and used as an independent EEPROM-like data memory.In addition to the 72 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM, the devices can address up to 64 KByte of external program memory andup to 64 KByte of external RAM.

The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST's devices. During poweron reset, the SST89E516RD2-40-C-NJEs can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation.The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The SST89E516RD2-40-C-NJEs are pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the user's reference and convenience only; SST does not guarantee its functionality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.