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ST10F271Z1

Features: 16-bit CPU with DSP functions 31.25 ns instruction cycle time at 64MHz max CPU clock Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator Enhanced boolean bit manipulations Single-cycle context switching support On-chip memories 128 Kbyte Flash memory (32-b...

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SeekIC No. : 004506161 Detail

ST10F271Z1: Features: 16-bit CPU with DSP functions 31.25 ns instruction cycle time at 64MHz max CPU clock Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator Enhanced boolean bit ...

ST10F271Z1 Data Sheet

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Part Number:
ST10F271Z1
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
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Product Details

Description



Features:

16-bit CPU with DSP functions
    31.25 ns instruction cycle time at 64MHz max CPU clock
    Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
    Enhanced boolean bit manipulations
    Single-cycle context switching support
On-chip memories
    128 Kbyte Flash memory (32-bit fetch)
    Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles.
    Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C)
    2 Kbyte internal RAM (IRAM)
    10 Kbyte extension RAM (XRAM)
    Programmable external bus configuration & characteristics for different address ranges
    Five programmable chip-select signals
    Hold-acknowledge bus arbitration support
Interrupt
    8-channel peripheral event controller for single cycle interrupt driven data transfer
    16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns
Timers
    Two multi-functional general purpose timer units with 5 timers
Two 16-channel capture / compare units
4-channel PWM unit + 4-channel XPWM
A/D converter
    24-channel 10-bit
    3µs minimum conversion time
Serial channels
    Two synch. / asynch. serial channels
    Two high-speed synchronous channels
    One I2C standard interface
2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version)
Fail-safe protection
    Programmable watchdog timer
    Oscillator watchdog
On-chip bootstrap loader
Clock generation
    On-chip PLL with 4 to 8 MHz oscillator
    Direct or prescaled clock input
Real-time clock and 32 kHz on-chip oscillator
Up to 111 general purpose I/O lines
    Individually programmable as input, output or special function
    Programmable threshold (hysteresis)
Idle, power-down and stand-by modes
Single voltage supply: 5V ±10%


Pinout

Connection Diagram


Specifications

Symbol Parameter Values Unit
VDD Voltage on VDD pins with respect to ground (VSS) -0.5 to +6.5 V
VSTBY Voltage on VSTBY pin with respect to ground (VSS) -0.5 to +6.5 V
VAREF Voltage on VAREF pins with respect to ground (VSS) -0.3 to VDD V
VAGND Voltage on VAREF pins with respect to ground (VSS) VSS V
VIO Voltage on any pin with respect to ground (VSS) -0.5 to VDD + 0.5 V
IOV Input current on any pin during overload condition ± 10 mA
ITOV Absolute sum of all input currents during overload condition | 75 | mA
TST Storage temperature -65 to +150 °C
ESD ESD Susceptibility (Human Body Model) 2000 V


Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.

During Power-on and Power-off transients (including Standby entering/exiting phases), the relationships between voltages applied to the device and the main VDD shall be always respected. In particular power-on and power-off of VAREF shall be coherent with VDD transient, in order to avoid undesired current injection through the on-chip protection diodes.




Description

The architecture of the ST10F271Z1 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F271Z1.




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