Telecom Line Management ICs FSK powerline transceiver
ST7540: Telecom Line Management ICs FSK powerline transceiver
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| Product : | Modem Chip | Supply Voltage - Max : | 5.25 V, 13.5 V |
| Supply Voltage - Min : | 4.75 V, 7.5 V | Supply Current : | 3.5 mA, 54 mA |
| Maximum Operating Temperature : | + 85 C | Minimum Operating Temperature : | - 40 C |
| Mounting Style : | SMD/SMT | Package / Case : | HTSSOP-28 |
| Packaging : | Tube |

|
Symbol |
Parameter |
Value |
Unit |
|
VCC |
Power supply voltage |
-0.3 to + 14 |
V |
|
VDD |
Digital supply voltage |
-0.3 to +5.5 |
V |
|
SVSS/GND |
Voltage between SVSS and GND |
-0.3 to +0.3 |
V |
|
VI |
Digital input voltage |
GND - 0.3 to VDD +0.3 |
V |
|
VO |
Digital output voltage |
GND - 0.3 to VDD +0.3 |
V |
|
IO |
Digital output current |
-2 to +2 |
MA |
|
Vsense, X2,PA_IN- ,PA_IN+, CL |
Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL Inputs |
SVSS - 0.3 to 5.6 |
V |
|
RX_IN |
Voltage range at RX_IN input |
-5.6 to 5.6 |
V |
|
TX_OUT, X1 |
Voltage range at TX_OUT, X1 outputs |
SVSS - 0.3 to 5.6 |
V |
|
PA_OUT |
Voltage range at powered PA_OUT Output |
VSS - 0.3 to +VCC +0.3 |
V |
|
I(PA_OUT) |
Power line driver output current (1) |
650 |
mArms |
|
TA |
Operating ambient temperature |
-40 to +85 |
|
|
TSTG |
Storage temperature |
-50 to 150 |
|
|
RxD, PA_OUT Pin |
Maximum withstanding voltage range Test condition: CDF-AEC-Q100-002- "Human Body Model" Acceptance criteria: "Normal Performance" |
±1750 |
V |
|
Other pins |
±2000 |
V |
The ST7540 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The ST7540 operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out and band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.