STP55NE06L

MOSFET TO-220 N-CH 60V 55A

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SeekIC No. : 00165148 Detail

STP55NE06L: MOSFET TO-220 N-CH 60V 55A

floor Price/Ceiling Price

Part Number:
STP55NE06L
Mfg:
STMicroelectronics
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Quick Details

Transistor Polarity : N-Channel Drain-Source Breakdown Voltage : 60 V
Gate-Source Breakdown Voltage : +/- 15 V Continuous Drain Current : 55 A
Resistance Drain-Source RDS (on) : 0.022 Ohms Configuration : Single
Maximum Operating Temperature : + 175 C Mounting Style : Through Hole
Package / Case : TO-220 Packaging : Tube    

Description

Transistor Polarity : N-Channel
Configuration : Single
Maximum Operating Temperature : + 175 C
Mounting Style : Through Hole
Packaging : Tube
Gate-Source Breakdown Voltage : +/- 15 V
Package / Case : TO-220
Drain-Source Breakdown Voltage : 60 V
Resistance Drain-Source RDS (on) : 0.022 Ohms
Continuous Drain Current : 55 A


Features:

* TYPICALRDS(on) = 0.018
* EXCEPTIONAL dV/dt CAPABILTY
* 100% AVALANCHE TESTED
* LOW GATE CHARGE 100
* HIGH dV/dt CAPABILITY
* APPLICATIONORIENTED
   CHARACTERIZATION



Application

* DC MOTOR CONTROL
* DC-DC & DC-AC CONVERTERS
* SYNCHRONOUS RECTIFICATION



Specifications

Symbol Parameter Value Unit
STP60NE06L STP60NE06LFP
VDS Drain-source Voltage (VGS = 0) 60 V
VDGR Drain- gate Voltage (RGS = 20 k) 60 V
VGS Gate-source Voltage ± 15 V
ID Drain Current (continuous) at Tc = 25 55 28 A
ID Drain Current (continuous) at Tc = 100 39 20 A
IDM(•) Drain Current (pulsed) 220 220 A
Ptot Total Dissipation at Tc = 25 130 35 W
  Derating Factor 0.86 0.23 W/
VISO Insulation Withstand Voltage (DC) - 2000 V
dv/dt Peak Diode Recovery voltage slope 7 V/ns
Tstg Storage Temperature -65 to 175
Tj Max. Operating Junction Temperature 175



Description

This STP55NE06L Power Mosfet is the latest development of SGS-THOMSON unique "Single Feature Size" process whereby a single body is implanted on a strip layout structure. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.




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