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SUD50N02-06P

Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.4 V On-State Drain Currentb ID(on) VDS =5 V, VGS = 10 V 964 A Drain-S...

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SeekIC No. : 004509219 Detail

SUD50N02-06P: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...

SUD50N02-06P Data Sheet

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SUD50N02-06P
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Description



Specifications

SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data		 Measured
Data		 Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.4 V
On-State Drain Currentb ID(on) VDS =5 V, VGS = 10 V 964 A
Drain-Source On-State Resistanceb rDS(on) VGS = 10V, ID = 20A 0.0041 0.0046
VGS = 10 V, ID = 20A, TJ = 125°C 0.0057
VGS = 4.5 V, ID = 20 A 0.0065 0.0073
Forward Voltageb VSD IS= 50A, VGS = 0 V 0.91 1.2 V
Dynamica
Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1 MHz 2418 2550 pF
Output Capacitance Coss 816 900
Reverse Transfer Capacitance Crss 348 415
Total Gate Chargec Qg VDS = 10 V, VGS = 4.5 V, ID =50A 20 19 nC
Gate-Source Chargec Qgs 7.5 7.5
Gate-Drain Chargec Qgd 6 6
Turn-On Delay Timec td(on) VDD = 10V, RL = 0.20
ID50A, VGEN = 10 V, RG = 2.5 		11 11 ns
Rise Timec tr 10 10
Turn-Off Delay Timec td(off) 9 24
Fall Timec tf 9 9

Source-Drain Reverse Recovery Time

trr

IF = 50 A, di/dt = 100 A/µs

31

35

Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width 300 µs, duty cycle 2%.
c. Independent of operating temperature.




Description

The attached spice model of SUD50N02-06P describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUD50N02-06P is best fit at the gate bias near the threshold voltage.

A novel gate-to-drain feedback capacitance network of SUD50N02-06P is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUD50N02-06P.



SUD50N02-06P N-Channel 20-V (D-S) 175C MOSFET




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