SUM110N08-05

Features:

•  N-Channel Vertical DMOS
•  Macro Model (Subcircuit Model)
•  Level 3 MOS
•  Apply for both Linear and Switching Application
•  Accurate over the −55 to 125°C Temperature Range
•  Model the Gate Charge, Transient, and Diode Reverse Recovery
    Characteristics


Description

The attached spice model of SUM110N08-05 describes the typical electrical characteristics of the n-channel vertical DMOS.  The subcircuit model is extracted and optimized over the  −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM110N08-05 is best fit at the gate bias near the threshold voltage. 
 
A novel gate-to-drain feedback capacitance network of SUM110N08-05 is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model.  All model parameter values are optimized to provide a best fit  to the measured electrical data and are not intended as an exact physical interpretation of the SUM110N08-05.