Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 2.1 V On-State Drain Currenta ID(on) VDS 5 V, VGS = 10 V 865 A Drain-So...
SUM110N08-07L: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...
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Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test C...
| SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
| Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
| Static | |||||
| Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 2.1 | V | |
| On-State Drain Currenta | ID(on) | VDS 5 V, VGS = 10 V | 865 | A | |
| Drain-Source On-State Resistancea | rDS(on) | VGS = 10V, ID = 30A | 0.0056 | 0.0055 | Ω |
| VGS = 10 V, ID = 30A, TJ = 125°C | 0.0089 | ||||
| VGS = 10 V, ID = 30A, TJ = 175°C | 0.011 | ||||
|
VGS = 4.5V, ID = 20A |
0.0076 | 0.0075 | |||
| Forward Voltagea | VSD | IF= 110A, VGS = 0 V | 0.93 | 1 | V |
| Dynamicb | |||||
| Input Capacitance | Ciss | VGS = 0 V, VDS = 25 V, f = 1 MHz | 4700 | 4420 | pF |
| Output Capacitance | Coss | 678 | 700 | ||
| Reverse Transfer Capacitance | Crss | 330 | 310 | ||
| Total Gate Chargec | Qg | VDS = 30V, VGS = 10 V, ID =110A | 82 | 81 | nC |
| Gate-Source Chargec | Qgs | 20 | 20 | ||
| Gate-Drain Chargec | Qgd | 20 | 20 | ||
| Turn-On Delay Timec | td(on) | VDD = 30V, RL = 0.47Ω ID110A, VGEN = 10 V, RG = 2.5 Ω |
19 | 15 | ns |
| Rise Timec | tr | 12 | 20 | ||
| Turn-Off Delay Timec | td(off) | 18 | 40 | ||
| Fall Timec | tf | 16 | 15 | ||
| Source-Drain Reverse Recovery Time | trr | IF = 110A, di/dt = 100 A/µs | 31 | 55 | |
The attached spice model of SUM110N08-07L describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM110N08-07L is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUM110N08-07L is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM110N08-07L.