SY100E142

The SY10/SY100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The SY100E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, accept parallel input data, while S-IN accepts serial input data.

The SEL (Select) control pin serves to determine the mode of operation, either SHIFT or LOAD. The shift direction of SY100E142 is from bit 0 to bit 8. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. Shifting is also performed on the rising edge of either CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR.

The SY100E142 is designed for applications such as diagnostic scan registers, parallel-to-serial conversions and is also suitable for byte-wide parity.