SY100EL15

1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at: 100EL15 Series: 4.2V to 5.5V.,10EL15 Series 4.75V to 5.5V.

The SY10/SY100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to VCC via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under singleended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

The SY100EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input.

The common enable (EN) SY100EL15, is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.