SY100EL33/L

The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the V_BB output should be bypassed to ground with a 0.01F capacitor. Also note that the VBB is designed to be used as an input bias on the SY100EL32V only; the V_BB output has limited current sink and source capability.

The reset pin of SY100EL32V is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset input allows for the synchronization of multiple EL33/Ls in a system.