SY100S336A

The SY100S336A is functionally the same as the SY100S336, but has Sn to TC  speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. down resistors. speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL  systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP , CET ) are provided. The CET  input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation.

When the SY100S336A is in the counting mode, the Terminal Count (TC ) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity of SY100S336A provided by the TC/Q3 output and the D0/CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow initialization of the counter by entering data in parallel to preset the counter.  A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 75KΩ pull-down resistors.