SY10E196

The SY10E196/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications.

The delay section of SY10E196 consists of a chain of gates and a linear ramp delay adjustment organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the SY10E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent.

The FTUNE input takes an analog coltage and applies SY10E196 to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the SY10E196 from the E195.

An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic of SY10E196 allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.