SY10E446

The SY10E446/100E446 are integrated 4-bit parallel-toserial data converters. These devices are designed to operate for NRZ data rates of up to a minimum of 1.3Gb/ s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. A serial input is provided to cascade two E446 devices for 8-bit conversion applications.

The SYNC input orf SY10E446 will asynchronously reset the internal clock circuitry. This pin allows the user to reset the internal clock conversion unit and, thus, select the start of the conversion process.

The MODE input is used to select the conversion mode of the SY10E446. With the MODE input LOW (or open) the device will function as a 4-bit converter. When the mode input is driven HIGH, the internal load clock will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E446s. When cascaded in an 8-bit conversion scheme, the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E446.

For lower data rate applications, SY10E446, a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01F capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal.