SY10E451

The SY10E451/100E451 offer six D-type flip-flops with singleended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input.

A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW. The VBB output is provided for use as a reference voltage for single-ended reception of ECL signals to that SY10E451 only. When used for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor.