Features: 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications Symbol Parameter Value Unit VCC Power Supply Voltage 0.5 to +7.0 V VI PECL Input Vo...
SY10ELT23: Features: 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications ...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...

| Symbol | Parameter | Value | Unit |
| VCC | Power Supply Voltage | 0.5 to +7.0 | V |
| VI | PECL Input Voltage | 0V to VCC+0.5 | V |
| VO | Voltage Applied to Output at HIGH State | 0.5 to +5.5 | V |
| IO | Current Applied to Output at LOW State |
Twice the Rated IOL |
mA |
| Tstore | Storage Temperature | 65 to +150 | °C |
| TA | Operating Temperature | 40 to +85 | °C |
The SY10ELT23/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew dual gate design of the ELT23 makes SY10ELT23 ideal for applications which require the translation of a clock and a data signal.
The ELT23 is available in both ECL standards: the SY10ELT23 is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.