SY10H607

The SY10H607/100H607 are 6-bit, registered, dual supply PECL-to-TTL translators. The devices feature differential PECL inputs for both data and clock. The TTL outputs feature 48mA sink, 15mA source drive capability for driving high fanout loads. The asynchronous master reset control is a PECL level input.

With its differential PECL inputs and TTL outputs, the SY10H607 device is ideally suited for the receive function of a HPPI bus-type board-to-board interface application. The on-chip registers simplify the task of synchronizing the data between the two boards.

The device is available in either ECL standard: the SY10H607 device is compatible with 10K logic levels, while the 100H device is compatible with 100K logic levels.