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Si1907DL

DescriptionThe attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model Si1907DLis extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance Si1907D...

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Si1907DL: DescriptionThe attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model Si1907DLis extracted and optimized over the −55 to 125...

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Part Number:
Si1907DL
Supply Ability:
5000

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  • 1~5000
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Description



Description

The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model Si1907DL is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance Si1907DL is best fit at the gate bias near the  threshold voltage.

A novel gate-to-drain feedback capacitance network of Si1907DL is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values of Si1907DL are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.




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