Si4921DY

Features:

P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125 Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics


Description

The attached spice model Si4921DY describes the typical electrical characteristics of the p-channel vertical DMOS.  The subcircuit model is extracted and optimized over the -55 to 125 temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.

A novel gate-to-drain feedback capacitance network Si4921DY is used to model the gate charge characteristics while avoiding convergence difficulties of the switched C_gd  model.  All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.