Si5311

· Performs Clock Multiplication to One of Four Frequency Ranges: 150–167 MHz, 600–668 MH,1.2–1.33 GHz, or 2.4–2.67 GHz
· Jitter Generation as low as 0.5 psRMS for 622 MHz Output
· Accepts Input Clock from 9.4–668 MHz
· Regenerates a “Clean”, Jitter-Attenuated Version of Input Clock
· DSPLL™ Technology Provides Superior Jitter Performance
· Small Footprint: 4 mm x 4 mm
· Low Power: 310 mW typical

Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional peration should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The Si5311 is a fully integrated high-speed clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. When the clock multiplier is operating in either the 150167 MHz range or the 600668 MHz range, the clock regenerator operates simultaneously. The clock regenerator creates a "clean" version of the input clock by using the clock synthesis phaselocked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges. The Si5311 uses Silicon Laboratories patented DSPLL™ architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs. The Si5311 represents a new standard in low jitter, small size, low power,and ease-of-use for high speed clock devices. It operates from a single 2.5 V supply over the industrial temperature range (40°C to 85°C).