TM54S816T

      The TM54S816T is organized as 4-bank*2097152-word*16-bit(8M*16),fabricated with high performance CMOS technology.Sychronous desigh allows precise cycle control with use of system clock I/O transactions are possible on every clock cycle.Range of operating frequencies,programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwith,high performance memory system applications.
      Here you can get some information about the features.First is that it is JEDEC  PC133/PC100 compatible.The second is single 3.3 V power supply.Next is LVTTL signal compatible.The fifth one are programmble CAS latency (3 or 2 clocks),programmble burst length (1,2,4,8 and full page) and programmble burst type (sequential and interleave).The sixth is burst read/write and burst read/single write operations capability.The seventh one is byte control (DQML and DQMU).The eighth one is auto and self refresh.The ninth one is 64 ms refresh period (4K Refresh).The last one is fully synchronous operation referenced to clcok rising edge.
      What comes next is the absolute maximum ratings of TM54S816T (V_SS=0 V).The voltage on any pin relative to V_SS (V_IN,V_OUT) is from -0.5 to 4.6 V.The voltage supply relative to V_SS (V_dd,V_ddQ) is from -0.5 to 4.6 V.The operating temperature (T_opr) is from 0 to +70.The power dissipation (PD) is 1 W.The output shorted current (I_OS) is 50 mA.
Then is about the DC operating conditions (V_SS=0 V,T_A=0 to 70).The minimum power supply voltage (V_dd,V_ddQ) is 3.0 V ,the typical is 3.3 V and the maximum is 3.6 V.The minimum input logic high voltage (V_IH) is 2.0 V and the maximum is V_dd V.The minimum input logic low voltage (V_IL) is -0.3 V and the maximum is 0.8 V.The minimum output logic high voltage (V_OH) is 2.4 V.The maximum output logic low voltage (V_OL) is 0.4 V.The minimum input/output leakage current (I_IL,I_OL) is -5A and the maximum is 5A.