Features: •fully functional decoder using a single 16 Mbit external SDRAM•accepts transport bit-streams of up to 72.8Mbps burst rate (60 Mbps average over one transportpacket)•on-chip European Common Descrambler hardware•hardware CRC accelerator for SI/PSI information proce...

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TMS320AV7110: Features: •fully functional decoder using a single 16 Mbit external SDRAM•accepts transport bit-streams of up to 72.8Mbps burst rate (60 Mbps average over one transportpacket)•on-c...

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Upload time: 2024/4/23

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Product Details



•fully functional decoder using a single 16 Mbit external SDRAM
•accepts transport bit-streams of up to 72.8Mbps burst rate (60 Mbps average over one transportpacket)
•on-chip European Common Descrambler hardware
•hardware CRC accelerator for SI/PSI information processing
•video decoder that decodes MPEG-1 and MPEG-2 Main Profile@Main Level bit-streams
•audio decoder that decodes MPEG-1 Layer I and II and the basic stereo channels from MPEG-2 Multi-channel bit-streams
•audio outpuin both PCM and SPDIF foats
•OSD processor that enables mixture of OSD and video data with transparency
•BitBLT hardware that accelerates memory block move
• 32/16 bit ARM/Thumb processor that removes the need of another CPU in the set-top box
•firmware that controls device operation and provides application access to hardware resources
•on-chip NTSC/PAL encoder that incorporates MacroVision logic for anti-taping protection
•analog Y/C or RGB, and Composite video outputs with 9-bit precision
•internally or externally generated video sync signals
•on-chip SDRAM controller for 16, 20, or 32 Mbit SDRAM
•general purpose 16-/32-bit Extension Bus Interface (EBI)
•a configurable high speed data interface to connect to either an IEEE 1394 link device, an IEEE1284 interface, or an external DMA device like SCSI that supports up to 16 Mbps data rate
•two 4-wire UART data ports supporting up to 115.2Kbps rate, and one 2-wire UART data portsupporting up to 9.6Kbps rate
•ISO 7816-3/NDC Smart Card interface
•I2C master/slave interface
•a programmable IR input port
•a programmable IR output port
• four dedicated general purpose I/O pins and five multiplexed pins which can be configured to begeneral purpose I/O pins
•2.5 volt device with 3.3 volt I/O


Figure 3 shows the high level block diagram of the complete software system. At the lowest level, eachhardware component has a firmware module associated with it. A module may consist of:
•Initialization code - executed at processor reset
•Interrupt Service Routines - executed from interrupt by the associated hardware module
The run-time support library provides an application programming interface for the user applicationsoftware. All run-time modules are written to be invoked from supervisory mode. This prevents software running in user mode from interfering with the built-in firmware.Functionally, the firmware consists of several software processes that are self contained at runtime and operate for the most part, independently and asynchronously. Because of the nature of the processing of a complex input stream, the processes are interrupt driven. The interrupt priorities determine the processing sequence, and the de-multiplexed input stream packet information determines the data path through the system. There is only minimal inter-process dependency, which eliminates the need for a software control-flow process. Any inter-process dependencies can be handled by proper structuring of the interrupt process in terms of priorities and multi-level processing.


The TPP can filter up to 32 different PIDs at any one time. All packets requiring further processing or containing relevant data are sent by the TPP to the internal Data RAM.  The TPP also activates or deactivates the European Common Descrambler (ECD) hardware based on the content of individual packets or under the CPU control. Up to 16 pairs of Conditional Access(CAkeys are stored in the TPP.  The data transfer from TPP to theinternal Data RAM is done via DMA automatically. Transport packets containing only audio or video payloadsareautomatically transferred to the proper external SDRAM memory buffer space via DMA. Other packets that require further processing are transferred to the CPU buffer, and an FIQ is issued to the CPU. Within the interrupt service routine, the firmware checks the FIFO that contains packets for further processing.  It then performs the necessaryparsing, removes the header portion, and establishes a DMA for transferring payload data from internal Data RAM to the appropriate destination.

The TPP also detects packets lost from the transport stream. Together with error concealment by the audio/video decoder, the TPP minimizes the effect of lost data. Along with the CPU, the TPP handles Program Clock Reference (PCR) recovery to control the external VCXO.  The TPP latches and transfers to the CPU its internal system clock upon the arrival ofanypacketcontaining a PCR.  Firmware, through an interrupt handling routine (FIQ), performs minimal filtering of the PCRs to control the external 27MHz VCXO.  Application software can perform more extensive filtering.  Figure 8 shows an example circuit for the external VCXO.  The output from the 'AV7110 is a pulse width modulated signal with a resolution of 256 levels. 

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