TMS470R1VF689 Selling Leads, Price trend, TMS470R1VF689 DataSheet download, circuit diagram from SeekIC.com

Features: `High-Performance Static CMOS Technology`TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™) 24-MHz System Clock (48-MHz Pipeline Mode) Independent 16/32-Bit Instruction Set Open Architecture With Third-Party Support Built-In Debug Module`Integrated Memory (VF689 only) 384K-Byte Program Flas...

Product Details

Description

Features:

`High-Performance Static CMOS Technology
`TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
24-MHz System Clock (48-MHz Pipeline Mode)
Independent 16/32-Bit Instruction Set
Open Architecture With Third-Party Support
Built-In Debug Module
`Integrated Memory (VF689 only)
384K-Byte Program Flash
Three Banks With 18 Contiguous Sectors
16K-Byte Static RAM (SRAM)
`Integrated Memory (VF688 only)
256K-Byte Program Flash
Two Banks With 14 Contiguous Sectors
12K-Byte Static RAM (SRAM)
`Operating Features
Core Supply Voltage (V_CC): 1.71 V - 2.05 V
I/O Supply Voltage (V_CCIO): 3.0 V - 3.6 V
Low-Power Modes: STANDBY and HALT
Industrial/Automotive Temperature Ranges
`470+ System Module
32-Bit Address Space Decoding
Bus Supervision for Memory and Peripherals
Analog Watchdog (AWD) Timer
Enhanced Real-Time Interrupt (RTI)
System Integrity and Failure Detection
`Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
`Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
Multiply-by-4 or -8 Internal ZPLL Option
ZPLL Bypass Mode
`Ten Communication Interfaces:
Two Serial Peripheral Interfaces (SPIs)
255 Programmable Baud Rates
Two Serial Communication Interfaces (SCIs)
2²⁴ Selectable Baud Rates
Asynchronous/Isosynchronous Modes
Two Standard CAN Controllers (SCC)
16-Mailbox Capacity
Fully Compliant With CAN Protocol, Version 2.0B
Class II Serial Interface (C2SIb)
Normal 10.4 Kbps and 4X Mode 41.6 Kbps
Three Inter-Integrated Circuit (I2C) Modules
Multi-Master and Slave Interfaces
Up to 400 Kbps (Fast Mode)
7- and 10-Bit Address Capability
`High-End Timer (HET)
12 Programmable I/O Channels:
12 High-Resolution Pins
High-Resolution Share Feature (XOR)
High-End Timer RAM
64-Instruction Capacity
`External Clock Prescale (ECP) Module
Programmable Low-Frequency External Clock (CLK)
`12-Channel 10-Bit Multi-Buffered ADC (MibADC)
32-Word FIFO Buffer
Single- or Continuous-Conversion Modes
1.55 s Minimum Sample and Conversion Time
Calibration Mode and Self-Test Features
`Flexible Interrupt Handling
`Expansion Bus Module (EBM) (PGE only)
Supports 8- and 16-Bit Expansion Bus Memory Interface Mappings
40 I/O Expansion Bus Pins
`55 Dedicated General-Purpose I/O (GIO) Pins and 39 Additional Peripheral I/Os (PGE Suffix))
`14 Dedicated GIO Pins and 39 Additional Peripheral I/Os (PZ Suffix)
`Eight External Interrupts
`Compatible ROM Device (Planned)
`On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1⁽¹⁾ (JTAG) Test-Access Port
`144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix)
`100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)
`Development System Support Tools Available
Code Composer Studio™ Integrated Development Environment (IDE)
HET Assembler and Simulator
Real-Time In-Circuit Emulation
Flash Programming

Pinout

Connection Diagram

Specifications

Supply voltage ranges: V_CC⁽²⁾ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . −0.5 V to 2.4 V
Supply voltage ranges: V_CCIO, V_CCAD, V_CCP (Flash pump) ⁽²⁾ . . . . . . . . . . . . −0.5 V to 4.1 V
Input voltage range: All 5 V tolerant input pins. . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.0 V
All other input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input clamp current: All 5 V tolerant pins,PORRST, TRST, TEST and TCK (V_I < 0) . . . −20mA⁽³⁾ADIN[0:11] I_IK (V_I < 0 or V_I> V_CCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
All other pins I_IK (V_I < 0 or V_I> V_CCIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ±20 mA
Operating free-air temperature ranges, T_A: A version . . . . . . . . . . . . . . . . . . . . .−40 to 85
Q version . . . . . . . . . . . . . . . .. . . .−40 to 125
Operating junction temperature range, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40 to 150
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40 to 150
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to their associated grounds.
3

Description

The TMS470R1VF689/VF688⁽¹) devices are members of the Texas Instruments TMS470R1x family of generalpurpose16/ 32-bit reduced instruction set computer (RISC) microcontrollers. The VF68x microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF68x utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The VF68x RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The TMS470R1VF689 devices contain the following:
·ARM7TDMI 16/32-Bit RISC CPU
·TMS470R1x system module (SYS) with 470+ enhancements
·384K-byte Flash (VF689 only)
·256K-byte Flash (VF688 only)
·16K-byte SRAM (VF689 only)
·12K-byte SRAM (VF688 only)
·Zero-pin phase-locked loop (ZPLL) clock module
·Analog watchdog (AWD) timer
·Enhanced real-time interrupt (RTI) module
·Two serial peripheral interface (SPI) modules
·Two serial communications interface (SCI) modules
·Two standard CAN controllers (SCC)
·Class II serial interface (C2SIb)
·Three inter-integrated circuit (I2C) modules
·10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
·High-end timer (HET) controlling 12 I/Os
·External Clock Prescale (ECP)
·Expansion Bus Module (EBM)
·Up to 87 I/O pins and 1 input-only pin (PGE Suffix), up to 51 I/O pins and 1 input-only pin (PZ Suffix)

The functions performed by the 470+ system module (SYS) include:
·Address decoding
·Memory protection
·Memory and peripherals bus supervision
·Reset and abort exception management
·Prioritization for all internal interrupt sources
·Device clock control
·Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the VF68x has the option to be driven by the oscillator clock. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The TMS470R1VF689 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

TMS470R1VF689

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