TP8472

DescriptionThe TP8472 3D Mouse Controller is specially designed to control 3D PS/2 mouse device. This single chip can interface three key-switches and six photo-couples direct to 8042. TP8472 can receive command and echo status or data format which are compatible with IBM PS/2 mode mouse and Micro...

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SeekIC No. : 004525936 Detail

TP8472: DescriptionThe TP8472 3D Mouse Controller is specially designed to control 3D PS/2 mouse device. This single chip can interface three key-switches and six photo-couples direct to 8042. TP8472 can re...

floor Price/Ceiling Price

Part Number:
TP8472
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Description

The TP8472 3D Mouse Controller is specially designed to control 3D PS/2 mouse device. This single chip can interface three key-switches and six photo-couples direct to 8042. TP8472 can receive command and echo status or data format which are compatible with IBM PS/2 mode mouse and Microsoft 3D PS2 mouse.Key debouncing circuit is provided to prevent false entry and improve TP8472 accuracy.In the conventional mouse, a great number of noises are generated when the grid is partially closed or opened.These noises are usually mistaken for movement signals by conventional mouse controller and the cursor of the display screen is thus moved frequently up and down or back and forth.

Features of the TP8472 are:(1)being compatible with 2D & 3D mouse mode; (2)including buyer testing mode; (3)built-in noise immunity circuit; (4)low power dissipation; (5)clocked by RC oscillating circuit or external oscillator; (6)three key-switches and six photo-couples inputs; (7)both key-press and key-release debounce interval 11 ms; (8)through three key-switch inputs, TP8472 can exert seven different output; (9)improved ESD protection; (10)built-in auto-reference function.

The absolute maximum ratings of the TP8472 can be summarized as:(1)supply voltage:-0.3 to 6.5V;(2)power dissipation:500mW;(3)storage temperature:-65 to 150;(4)temperature under bias:0 to 70.System first check if TP8472 is transmitting data. If TP8472 is transmitting, the system can override the output by forcing CLK to an inactive level prior to the tenth clock. If the transmission of TP8472 beyond the tenth clock ,the system must receive the data.If it is not transmitting or if the system choose to override the output, the system force CLK to an inactive level for a period of not less than 100u sec while preparing for output. When the system is ready to output startbit (0), it allows CLK to go to active level.If request-to-send is detected, TP8472 clocks in 11 bits. Following the tenth clock, it checks for an active level on the DATA line, and if found, force DATA low,and clock once more.




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