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Part Number: TSPC750A
Description: The TSPC750A and TSPC740A microprocessor(after named 750A/740Aare lowpower implementations of th...
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TSPC750A
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DataSheet
General Description
TSPC750A General Description
The TSPC750A and TSPC740A microprocessor (after named 750A/740Aare lowpower implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture.
The 750A/740A microprocessors' designs are superscalar, capable of issuing three instructions per clock cycle into six independent execution units.
The 740A/750A microprocessors use a 2.6/3.3V CMOS process technology and maintain full interface compatibility with TTL devices.
The 750A/740A provide four software controllable power-saving modes and a thermal assist unit management.
The 750A/740A microprocessors have separate 32K byte, physically addressed instruction and data caches and differ only in that the 750A features a dedicated L2
cache interface with L2 on-chip tags.
Both are software and bus-compatible with the PowerPC 603™ and PowerPC 604™ families, and are fully JTAG compliant.
The TSPC740A microprocessor is pin compatible with the TSPC603e family.
TSPC750A Maximum Ratings
| Characteristic | Symbol | Maximum Value | Unit |
| Core supply voltage | VDD | -0.3 to 2.75 (4) | V |
| PLL supply voltage | AVDD | -0.3 to 2.75 (4) | V |
| L2 DLL supply voltage | L2AVDD | -0.3 to 2.75 (4) | V |
| 60x Bus supply voltage | OVDD | -0.3 to 3.6 (3.5) | V |
| L2 Bus supply voltage(3) | L2OVDD | -0.3 to 3.6 (3.5) | V |
| Input voltage | Vin | -0.3 to 3.6 (2) | V |
| Storage temperature range | Tstg | -55 to 150 | °C |
Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset.
3. Caution: OVDD must not exceed VDD/AVDD by more than 1.2V at any time including during power-on reset.
4. Caution: VDD/AVDD must not exceed OVDD by more than 0.4V at any time including during power-on reset.
5. Caution: VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 5.
TSPC750A Features
• 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz (TSPC750A) with 1 MB L2 at 133 MHz
• 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A)
• 488 MIPS at 266 MHz
• Selectable Bus Clock (11 CPU Bus Dividers up to 8x)
• PD Typical 4.2 W at 200 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Superscalar (3 Instructions per Clock Cycle)
• 4-GByte Direct Addressing Range
• 64-bit Data and 32-bit Address Bus Interface
• 32 KB Instruction and Data Cache
• Six Independent Execution Units and Two Register Files
• Write-back and Write-through Operations
• fint max = 266 MHz
• fbus max = 83.3 MHz
• Compatible CMOS Input / TTL Output
• 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A)
• 488 MIPS at 266 MHz
• Selectable Bus Clock (11 CPU Bus Dividers up to 8x)
• PD Typical 4.2 W at 200 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Superscalar (3 Instructions per Clock Cycle)
• 4-GByte Direct Addressing Range
• 64-bit Data and 32-bit Address Bus Interface
• 32 KB Instruction and Data Cache
• Six Independent Execution Units and Two Register Files
• Write-back and Write-through Operations
• fint max = 266 MHz
• fbus max = 83.3 MHz
• Compatible CMOS Input / TTL Output
TSPC750A
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- Datasheet: TSPC750A
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