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Part Number: TSPC860
Description: The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICC®) is a versatile one-chip inte...
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TSPC860
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General Description
TSPC860 General Description
The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICC®) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC (pronounced "quick") can be described as a PowerPC-based derivative of the TS68EN360 (QUICC™).
The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches. The communications processor module (CPM) of the TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface (TWI) compatible with protocols such as I2C. Moderate to high digital signal processing (DSP) functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (DRAMs). Overall system functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real-time clock.
TSPC860 Maximum Ratings
| Parameter | Symbol | Min | Max | Unit |
| I/O Supply Voltage | VDDH | -0.3 | 4.0 | V |
| Internal Supply Voltage | VDDL | -0.3 | 4.0 | V |
| Backup Supply Voltage | KAPWR | -0.3 | 4.0 | V |
| PLL Supply Voltage | VDDSYN | -0.3 | 4.0 | V |
| Input Voltage | VIN | -0.3 | 4.0 | V |
| Storage Temperature Range | TSTG | -65 | +150 | °C |
TSPC860 Features
• PowerPC® Single Issue Integer Core
• Precise Exception Model
• Extensive System Development Support
On-chip Watchpoints and Breakpoints
Program Flow Tracking
On-chip Emulation (Once) Development Interface
• High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)
• Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)
• MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks
• Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 * 32-bit Fixed Point Registers
Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution
4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU
Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line Granularity
MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs
MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB; 16 Virtual Address Spaces and 8 Protection Groups
Advanced On-chip Emulation Debug Mode
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)
• 32 Address Lines
• Fully Static Design
• VCC = +3.3V ± 5%
• fmax = 66 MHz
• Military Temperature Range: -55°C < TC < +125°C
• PD = 0.75 W Typical at 66 MHz
• Precise Exception Model
• Extensive System Development Support
On-chip Watchpoints and Breakpoints
Program Flow Tracking
On-chip Emulation (Once) Development Interface
• High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)
• Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)
• MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks
• Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 * 32-bit Fixed Point Registers
Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution
4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU
Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line Granularity
MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs
MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB; 16 Virtual Address Spaces and 8 Protection Groups
Advanced On-chip Emulation Debug Mode
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)
• 32 Address Lines
• Fully Static Design
• VCC = +3.3V ± 5%
• fmax = 66 MHz
• Military Temperature Range: -55°C < TC < +125°C
• PD = 0.75 W Typical at 66 MHz
TSPC860 Connection Diagram
TSPC860
PDF/DataSheet Download
- Datasheet: TSPC860
- File Size: 1639733 KB
- Manufacturer: ATMEL [ATMEL Corporation]
- Click here to Download
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