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TZA3004HL

Features: ` Data and clock recovery up to 622 Mbits/s (STM1/OC3 and STM4/OC12)` Differential data input with 2.5 mV peak-to-peak typical sensitivity` Differential CML (Current-Mode Logic) data and clock outputs with 50 driving capability` Adjustable CML output level` Loop mode for system testing`...

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SeekIC No. : 004534333 Detail

TZA3004HL: Features: ` Data and clock recovery up to 622 Mbits/s (STM1/OC3 and STM4/OC12)` Differential data input with 2.5 mV peak-to-peak typical sensitivity` Differential CML (Current-Mode Logic) data and c...

TZA3004HL Data Sheet

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Part Number:
TZA3004HL
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

` Data and clock recovery up to 622 Mbits/s (STM1/OC3 and STM4/OC12)
` Differential data input with 2.5 mV peak-to-peak typical sensitivity
` Differential CML (Current-Mode Logic) data and clock outputs with 50 driving capability
` Adjustable CML output level
` Loop mode for system testing
` BER related LOS detection
` Few external components needed
` LQFP48 plastic package
` Power dissipation typical 370 mW
` Single supply voltage.


Application

· Data and clock recovery in STM1/OC3 and STM4/OC12 transmission systems (up to 622 Mbits/s).


Pinout

Connection Diagram


Specifications

SYMBOL
PARAMETER
MIN.
MAX.
UNIT

VEE

 negative supply voltage -6 +0.5 V
Vn DC voltages
pins 3, 4, 6, 7, 21, 22, 33, 34, 42, 43, 45, 46
pins 1, 12, 39
pins 9, 24, 30, 37, 48
pins 15, 16
-1
VEE - 0.5
VEE - 0.5
VEE + 0.5
+ 0.5
+ 0.5
+ 0.5
- 0.5
V
V
V
V
In input current
pin 1
pins 21, 22, 33, 34
-
-20


1
+10


mA
mA

Ptot total power dissipation - 700 mW
Tamb ambient temperature -40 +85 °C
Tj junction temperature -40 +110 °C
Tstg storage temperature -65 +150 °C



Description

The TZA3004HL is a data and clock recovery IC intended for use in SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) systems.

The TZA3004HL circuit recovers data and extracts the clock signal from an incoming bitstream up to 622 Mbits/s. It can be configured for use in STM1/OC3 and STM4/OC12 systems.




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