U6218B-AFP

The U6218B-AFP has the following features including 1.3 GHz divide-by-8 prescaler integrated(can be bridged);EASY LINK INTERFACE to MOSMIC and MIXER-IC;Low power consumption(I:yp. 5 V/35 mA);Electrostatic protection according to MIL-STD 883 SO-16 small package.

The U6218B is programmed via 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pin 4,5,10 are used as SDA,SCL and address select inputs in FC-bus mode or as  data clock and enable inputs in 3-wire hus mode. The data of U6218B-AFP includes the scaling factor SF and switching output information. In IzC-bus mode there are some additional functions available(ADC, bidirectional ports, etc.).The input amplifier together with a divide-by-8 prescaler gives an excellent sensitivity(see 'TYPICAL PRESCALER INPUT SENSITIVITY').The input impedance is shown in the diagram 'TYPICAL INPUT IMPEDANCE'. When a new divider ratio according to the requested fvco is cntercd, the phase detector and charge pump together with the tuning amplifier U6218B-AFP adjusts the control voltage of the VCO until the output signals of the programmable divider and the reference divider are in frequency and phase locked. The reference frequency may be provided by an external source capacitively coupled into pin 2, or by using an on-board crystal with an 78pF capacitor in series. The crystal operates in the series resonance mode.

A typical application of U6218B-AFP is shown on page 15. All input/output interface circuits are shown on page 14.Some special features which are related to test- and alignment procedures for tuner production are explained in the following bus mode description.The programmable divider bytes PDB1 and PDS2 are controlling the division ratio of the 15 bit programmable divider. U6218B-AFP is loaded in a 15 bit latch after the 8th clock pulse of the second divider byte PDB2, the control and the port register latches are loaded after the 8th clock pulse of the control byte CB1 rcesp. port byte CB2.