U62256

a Stresses greater than those listed under „Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

b Maximum voltage is 7 V

c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

The U62256 is a static RAM manufactured using a CMOS process technology with the following operating modes:
                 - Read           - Standby
                 - Write          - Data Retention
The memory array is based on a MIXMOS cell.

The U62256 is activated by the falling edge of E. The address and control inputs open simultaneously.According to the information of W and G, the data inputs, or outputs,are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information read is available. The data outputs of U62256 have not preferred state.

The Read cycle of U62256 is finished by the falling edge of W, or by the rising edge of E, respectively.Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required.